As we evaluate the system-on-a-chip (SoC) design landscape, the industry continues to search for solutions to a long list of design challenges and issues. They include the following.
- Rising cost: SoC silicon and software design costs are rising at each new process node, with increasing emphasis now being placed on the software side of the design cost equation. How can we reduce design costs, especially for software, in a meaningful way?
- Design complexity: Complexity is increasing to meet rising market requirements. How can SoC designers continue to meet these rising demands without "breaking the bank" through higher design costs, or missing the market window altogether because of long design cycle times?
- Power consumption: This continues to be the major issue for designers today -- especially in light of the trend for users to have hundreds of apps on their mobile devices. What methods are available to reduce power consumption and still meet consumer expectations and market requirements?
- Integration cost: The cost to integrate the large number of IP blocks being used in SoCs today is rising, and this is probably one of the causes of increasing design costs in general. How can IP integration costs for complex SoC designs be curtailed or even lowered while still infusing added functionality into these designs?
- Testing and verification: The difficulty in achieving timing closure and running verification for complex SoC designs are other troubling trends designers must contend with. Are there any solutions today that reduce the level of effort needed to reach timing closure and that make the verification process easier?
- Return on investment: Rising design costs for SoCs increase the number of parts that need to be sold just to make back the design investment. How can SoC designers reduce the level of effort needed to create the system-level functionality needed for their silicon solutions and still reach performance and functionality targets set by the market?
- Performance and latency: The multicore era is firmly with us, and performance issues, especially in the area of memory latency, continue to get worse. Is there any solution on the horizon that can finally reduce memory latency and break the "memory bottleneck"?
- Efficiency issues: The number of IP blocks in complex SoC designs today is approaching 100, if it hasn't already exceeded that level. This adds to design complexity and cost. How can SoC designers test out different types of IP cost-effectively and efficiently?
- Identifying new markets and applications: Silicon foundries continue to push the process technology envelope at each new node, but the cost for doing so is rising as it becomes more difficult to advance. What new markets and applications will drive wafer starts at 20nm and at 14nm?
This is a pretty long list of issues and questions that the industry needs to work through. Many of them are not new, but it certainly feels as if they are becoming more intense in their nature and importance. This is one of the reasons Semico Research Corp. decided to host a conference on the IP ecosystem. Since IP has assumed such a critical role in the SoC design methodology today, Semico has created a forum that brings together concerned parties to discuss these issues, their impact on the industry, and their potential solutions.
The Semico Impact Conference, titled "Focus on the IP Ecosystem," is taking place on May 16 in San Jose, Calif. Speakers from across the industry will address some of the challenges and issues raised above.
EDA tool vendors, silicon foundries, FPGA vendors, IP vendors, and IDMs and OEMs will present their ideas about the path the industry is taking, or should take, to resolve these questions. All these companies are intimately involved in the IP ecosystem directly or are touched by it indirectly to the point that any potential solutions will probably start as ideas conceived in private but discussed in public, to gain insight into just what SoC designers and silicon architects are thinking about.
Just the topic of the trend towards IP subsystems alone could take up an entire day, given the complexity of the issues involved. The potential of IP subsystems to provide real solutions to some of the issues and questions listed above makes discussing this subject a real imperative for the industry. A healthy debate on these issues is necessary to gain industry consensus and support in order to chart a course that will provide the best possible outcome for all involved.
If you are a SoC designer and have an opinion about some of the questions listed here, you should attend, discuss, and learn what solutions are being proposed. Make your voice heard, and hear from others. If you are a silicon architect and wonder how you are going to be able to squeeze all the functionality needed into your next design in less time and at a lower cost, you should attend and help shape the future through your input and comments.
If you are a silicon or software engineer and have noticed how it is getting harder to keep coming up with new solutions to old problems, you should attend to find out what ideas are being proposed to actually help put some of these issues behind us. We think this conference will provide a vehicle for many concerned parties to come together and have the opportunity to hear about the problems that have been identified, what we should be prepared for, and learn about real solutions that can move the IP ecosystem forward toward potential resolution of these issues. That would be worth the price of admission alone.
We hope you agree and look forward to seeing you at the Doubletree Hotel in San Jose, Calif., on May 16. For more information on the conference visit Semico's Website, or register here.