Thanks for the reply. One point you made was interesting:
"It is very counterproductive to point fingers at different groups within a company when the esults are poor"
I think this is always an internal battle since teams are disparate in most organizations and feel accoutnable for their own tasks at the micro level and not necessarily the macro level as a whole organization. This has to be one of the biggest things that can throw a wrench in any product development's success. This is where a unified company culture is vital... and usually not stressed enough.
You ask a very interesting question. Today there are two sources of IP Subsystems - large IDMs that have created them internally and, just starting now, the 3rd Party IP market.
Large IDMs do not talk much about their internal efforts because they are being used to competitively differentiate their products from their competitors. A secondary result is to reduce the level of effort necessary to create the system-level functionality needed for thier complex SoC products. The 3rd Party IP vendors are just starting their marketing efforts.
To answer your question directly: no, there is no direct evidence that this approach has been implemented effectively. That is to say no one is trumpeting this result - yet.
Having said all that, I would like to point out that the large IDMs would not be pursuing this course if there were not tangible benefits to doing so. Companies like Intel, Qualcomm, Broadcom, ST Micro, Toshiba, TI and I suspect Apple as well, and many others, have all created their own IP Subsystems and use them in their design efforts. Although there is no direct evidence of how seamless the process is between the HW and SW teams, I think it safe to say that where there is some smoke there is probably some fire as well.
I would imagine that the process is not totally painless. There needs to be a willingness on both sides to collaborate to solve real issues and problems that prevent designs from being accomplished more efficiently and at less cost. I think if this approach is taken by all concenred, then great strides can be made in reducing the level of effort necessary to create the complex silicon solutions the market requires today.
To me, it is all about the silicon (meaning the final solution at the system level). If the silicon is not competitive in the market because the design was too expensive, or took too long to complete, or does not perform as expected or the software does not run as expected, then it is all but useless. It is very counterproductive to point fingers at different groups within a company when the esults are poor. The net result is that the product does not live up to expectations and everyone at that company suffers - even upper management!
I believe this is why the IP Subsystem concept has a chance of succeeding in the market. If implemented correctly and efficiently, it offers solutions to many of the issues I raised in the original post. Thre are other potential solutions for these issues, but they are more complex to implement and more costly. Here I am thinking of things like less leaky transistors, or better and more powerful tools for doing the design.
The problem with creating a better process technology or investing in better tools is that the industry is already doing that and has been doing that for at least the last 10 years, yet the problems are still with us and are arguably getting worse. The reason for this I believe is that these approaches are trying to hit a moving target that is accelerating as time goes on. A better approach is to allow design teams to craft their silicon solutions using larger pieces of the puzzle in the form of complete system-level functions and to allow the software teams to write the applications code specifically to each IP Subsytem. Then, assuming there is more than one IP Subsystem in the silicon, the applications can be written in parallel. This potentially can dramatically reduce both design time and cost while allowing better code to be written.
The devil is in the details. This approach will certainly not be easy but I believe it is possible if care is taken in how the infrastructure is created and if people are committed to getting this done.
I know this is a very long answer to a relatively short question, but as you can see, this issue is pretty complex.
What methods are available to reduce power consumption and still meet consumer expectations and market requirements?
@Rich, thanks for the post. One of the major changes that the companies are implementing is they are trying redefine the old architecture so that they can reduce the chip-area. I have seen many digital libraries where the companies have achieved as much as 40% reduction in power by redefining the architecture.
Rich, thanks for the detailed explanation. As you have clearly illustrated, this addresses most of the major issues when it comes to complete SoC system design. And it also releases the creativity from the software people.
One of the areas that we will discuss at the IP Ecosystem conference is the impact of IP Subsystem products on the SoC design flow. As you correctly point out, the software side of the SoC design equation has started to become the largest portion of the cost associated with these designs. One of the attractions to using IP Subsystems is the ability to write the software application that will be executed by that subsystem independently of the other applications to be created. Because the IP Subsystem is a complete system-level function (and not a collection of descrete IP blocks aggregated together), it is possible to write the software app before the silicon design is done. if there is more than one IP Subsystem in the design, then the software applications can be written in parallel. Based on current trends where software designers outnumber silicon designers on large SoC designs, I have to believe that the ability to write the software apps in parallel, and not serially, will allow total software design time to be reduced, this can reduce costs and accelerate time to market.
To your point about not having a stable SoC to write the application for: the IP Subsystem can stand in for large parts of the SoC since it is a system-level function that has already been tested (delivered with its own testbench) and could quite possibly come with application code already written for it. Take a look at the Audio IP Subsytem introduced by Synopsys at the end of March. It comes with >500K lines of application code. Other subsystem products are coming and they will probably come with their own application code as well. It depends on the function and what the function requires at the system level as to how many lines of code will be attached to the subsystem.
Thank you for your question, It goes to the heart of the issues surrounding the rising costs and complexity of the SoC design flow today. I am sure we will see other products that start to address these questions and issues - maybe announced at the conference!
Given the amount of challenges, it is really not easy to deliver a product on schedule to target specific market demand. In parallel to the SoC development, firmware, operating systems, software must come along. This is definitely problematic as there is no stable SoC yet for software development and hence the development process must come hand-in-hand.
EBN Dialogue enables and encourages you to participate in live chats with notable leaders and luminaries. Not only editors and journalists, but the entire EBN community is able to comment and ask questions. Listed below are upcoming and archived chats.
Thailand Stages a Comeback Join EBN contributor Jennifer Baljko on Thursday August 23, 2012, at 11:00 a.m. EST for a live chat on how electronic manufacturers in Thailand have shored up their supply chain to reduce the impact of future natural disasters.
Microsoft Surface: Potential Winners & Losers What are the implications for the electronics industry supply chain of Microsoft Corp.'s decision to launch its own tablet PC? Join industry veteran and EE Times' systems and OEM expert Rick Merritt on Tuesday, July 3, at 12:00 pm EDT for a Live Chat on this subject.
Join EBN contributor Jennifer Baljko on Thursday August 23, 2012, at 11:00 a.m. EST for a live chat on how electronic manufacturers in Thailand have shored up their supply chain to reduce the impact of future natural disasters.
Peter Drucker famously said "Trying to predict the future is like trying to drive down a country road at night with no lights while looking out the back window." Yet in the razor's-edge world of electronics—with a lean supply chain and just-in-time demands—the need to know the future is vital.
While no one really can accurately predict the future, we can take guidance from another Drucker saying which is the best way to predict the future is to create it.
You've heard the saying "the No. 1 supply chain risk is your people." That hasn't always been the case. But today's complex global supply chain requires a new type of multitalented employee. It's one who understands, finance, marketing, economics, is savvy with technology, graceful with relationships and can think analytically.
Where are these people? Are universities properly preparing the next generation supply chain professionals? How do train your existing workforce for these new, demanding positions?
Brian Fuller, editor-in-chief of EBN, will lead a 60-minute Avnet Velocity panel discussion that will ask and answer these and other questions swirling around today's supply-chain talent challenges.