28nm Issues Spark Debate at Semico Summit

At the {complink 7526|Semico Research Corp.} Summit held May 2, in Phoenix, Ariz., one of the more lively discussions occurred during the panel titled “Challenges at 28nm.” Mahesh Tirupattur, from Analog Bits, served as moderator on the panel, and he brought out the best from the audience, as well as the panel members.

The panelists included:

  • Chi-Ping Hsu, senior VP, Research & Development, Silicon Realization Group, Cadence
  • Mark Papermaster, Vice President, Switching Silicon Technology Group, Cisco Systems
  • Grant Pierce, President & CEO, Sonics
  • Suk Lee, Director, Design Infrastructure Marketing Division, TSMC

Chi Ping Hsu of Cadence believes the 28nm semiconductor manufacturing technology node is challenging because of the technical and economic problems that have steadily become worse in the 45nm process node. The electronics design automation (EDA) industry collectively must spend around $2 billion per year on R&D aimed at solving or removing obstacles to industry productivity, manufacturing predictability, and profitability, he said.

Despite these problems, TSMC currently has 89 28nm tape-outs completed or in progress, according to Suk Lee. In addition, TSMC is making a big investment and expects to pour $16 billion into 28nm development and capacity.

As vice president of Cisco's Switching Silicon Technology Group, Mark Papermaster has a firsthand view of ASIC design and strategy. Leakage power is now 50 percent of total power consumption, he said. Many mobile vendors think 28nm will allow them to reduce power consumption, but Papermaster believes 28nm is a very fundamental process node and that the industry requires a system level solution.

Grant Pierce of Sonics, meanwhile, said his company's role has changed over time. He agreed with Papermaster and said Sonics is now being asked to address issues with a system level approach. Customers want Sonics to operate more as a general contractor to pull the right types of IP together for particular designs.

Audience participation was fueled by a question and statement from Len Perham, president and CEO of Mosys, who argued that designing products at and below 28nm is very costly, even while overall chip performance is actually decreasing. “How can a company justify moving to 28nm when problems with yields and signal integrity reduce any scaling benefit?” he asked.

Grant Pierce of Sonics had a ready answer: “invest or die.” The solution is to decrease risk and make the process more predictable by getting the IP and tool sets early so that the needed collaboration and verification have an opportunity to run their course.

Aart de Geus, chairman and CEO at Synopsys, offered a more optimistic view. The same challenges and skepticism arose when the industry was transitioning from 65nm to 45/40nm, he said. The challenges were overcome through collaboration between engineers, designers, and manufacturers. De Geus believes the current concerns over 28nm are overblown and that scaling roadblocks will continue to be overcome for digital designs into the 16/14nm process node.

Grant Pierce agreed with de Geus that the roadblocks could be overcome but warned that the 28nm node will be a short-lived node. He predicted a “fab war” will break out with the transition to smaller nodes because designs in the mobile space are already looking to 22nm, to get even more power savings.

Another question from the audience focused on whether 3D represents an alternative to or an enabler to scaling?

The companies represented on the panel were definitely biased towards those with the ability to move to the next advanced technology solution. They benefit from the companies willing to move up the technology curve but there were many in the industry that can't afford to design at the bleeding edge, or even be fast followers.

Typically, when all the bugs are worked out and economies of scale are reached, there would be a group of fast followers providing a second wave of demand for the advanced IP, tools, and capacity. The concern today is whether the fast followers, or any followers, are willing and able to move quick enough to provide the panelists a return on their investment.

A possible solution to this Catch 22 situation is the increasing use of derivative SoC designs to reduce cost and time to market. However, over-reliance on derivative designs does not address the fact that many of the current SoC architectures are getting rather old.

A new round of effort to refresh these architectures must be started to ensure silicon solutions at 28nm can utilize all the features of 28nm, while at the same time delivering all the features and functionality the markets will demand.

Based on what we are seeing today, Semico believes the process of architectural refresh has started and that it will accelerate over the next two years.

8 comments on “28nm Issues Spark Debate at Semico Summit

  1. AnalyzeThis
    May 12, 2011

    I agree that there were similar challenges and skepticism when there was the transition from 65nm to 45/40nm.

    However, I'm not sure if I agree that 28nm will be short-lived… 28nm to 22nm doesn't seem to be as dramatic of an improvement as the 65nm to 45nm move for instance. Would making the transition AGAIN in such a relatively short period of time for some really be worth the additional power savings? Isn't it probably wiser to skip over 22nm in favor of 16/14nm?

    Unfortunately, I'm not enough of an expert in this space to answer that question… so I'm really interested to see what other people's thoughts are.

    Thanks for the article, Joanne, this is a subject I'm very interested in, but obviously have a lot to learn about!

  2. Anand
    May 12, 2011

    “Leakage power is now 50 percent of total power consumption, he said.”


     Can this leakage power be reduced using high-K dielectric materials or is this the optimal leakage power that we can achieve ?

  3. Joanne Itow
    May 12, 2011

    Dear anandvy,

    You are correct, High-K, Metal Gate (HKMG) is one of the technology advances that is helping to improve the power leakage issue at 32nm/28nm.  At 22nm Intel is the first to introduce a new transistor structure.  3D Tri-Gate transistors take us to a whole new level.    Technology marches on!



  4. Nemos
    May 12, 2011

    When we moved down from 65nm integration to 45nm we have seen a lot of new technology occurred such as new computer with powerful processors,smart phones, tablets, etc. If the electronic industry break the 45nm obstacle and manufacture Asic with 28nm integration, then new amazing technologies will occur.

    I hope we will see this to come soon, and we should not have to wait two years…

  5. Wale Bakare
    May 12, 2011

    High- K materials might fixed the leakage issue but it hasnt been proven practically. Being proposed by some research institutions – polymer ceramic nanocomposite material systems may be used in processing  to generate High – K such that value of K range between 80 and 200 @1MHz to 10GHz.


  6. Mydesign
    May 13, 2011

        Joanne, you are right. Power Leakage is a major concern and about 50% of the energy is going to be waste in 45nm process node. But in 28nm this power waste is very less and hence, the power efficiency can increase or power requirement can be decrease.  That would be one of the reason for increased  popularity of 28nm nodes.

  7. eemom
    May 13, 2011

    The move to 28nm is happening now.  Processor and mobile device makers are leading the charge as they did at 45nm and as they will again at 20nm.  The Fabs and EDA vendors will scramble to improve the yields and improve the tools to allow the design community to develop their end products (smart phones, tablets, PC's).  At this point in the 28nm life cycle, one of the gating factors is the development of IP (standard cell libraries, memories, cores) for the designers to use.  They will all converge as they have for every other node and the process will begin again (it already has).

  8. elctrnx_lyf
    May 23, 2011

    Definitely it is not true that 28nm is really complex and doesn't provide much yield The companies will not ivest without a strong information and their own experiments on the technology. But further down the line we need technologies like 3D and TSV to improve the power efficiency and smaller size.

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