MUNICH — The Internet of Things took a dominant role at the 2014 Electronica Show in Munich, Germany. Developing ultra-low-power nodes for sensors that can be connected wirelessly to the wider Internet is opening up many different design options, and both silicon and embedded software suppliers are developing a variety of architectural approaches.
New silicon from NXP, Cypress Semiconductor, and Atmel is reducing the power consumption and adding a range of new peripherals, including programmable logic. At the same time, new protocols are extending the range of the wireless nodes, reaching across the city of Munich.
New ways of connecting systems across the factory floor, the enterprise, and the home are being driven by other protocols, such as Thread, that were also demonstrated across the show.
Here are seven approaches to the IoT controller from Electronica 2014.
With the LCP54100, NXP aims to be the controller at the heart of sensor nodes. Combining an ultra-low-power 32-bit ARM 100MHz Cortex-M0+ core at 55 uW/MHz for managing peripherals and monitoring the system with a 100MHz ARM Cortex-M4 processor for complex algorithm handling, the $2 device is targeted directly at battery-powered sensor fusion applications.
NXP has created power profiles in ROM with an API to manage all the peripherals on the chip and the frequency and sleep modes of the cores, though these can also be adjusted directly.
The voltage is automatically adjusted between 0.85 V and 1.35 V to match the different frequency sets for each of the processor cores, depending on the power profiles.
Peripherals include a 12-bit ADC that operates across the battery range of 1.62 V to 3.6 V with a constant 4.8 Msample/s.
The 90nm 54100 includes 256 KB of flash and 104 KB of SRAM. Package options include a 3.3 x 3.3mm chip scale package. NXP has also partnered with Bosch Sensortec for Arduino shields of various sensors, and with Ackme for a Broadcom-based WiFI module.
Cypress Semiconductor's first single-chip Bluetooth Low Energy product includes headroom on its ARM M0+ controller for applications, as well as programmable logic to create dedicated custom state machines for an IoT node.
Cypress has taken a different approach to waking the chip up when there is a relevant signal, creating isolated op-amps that can be in a sleep mode until a signal is detected and then wake the 48MHz ARM Cortex M0+ controller core.
Peripherals include the PsoC CapSense touch controller, LCD driver, SAR data converter, two low-power comparators, and up to 128 KB flash and 16 KB SRAM
As you would expect, flexible low power modes run at 1.3 μA for the “Deep-Sleep” Current, 50 nA for the “Hibernate” Current, and 60 nA for the Stop Current.
However, what gives it more headroom is the PLD array that allows custom logic to be implemented without the need for the controller core. This reduces power consumption but makes a direct comparison of power figures difficult.
An on-chip balun also reduces the number of external components for the antenna design to just two. The chips are sampling in 68-ball CSP and 56-pin QFN packages, with production expected in December.
The latest 32-bit controller from Atmel has reached a new low-power standard for ARM Cortex-M0+ devices with power consumption down to 40 µA/MHz in active mode and 200 nA in sleep mode. The SAML21 includes a full-speed USB host and device, 12-bit analog, AES, and capacitive touch sensing for nodes that need battery life of up to a decade.
The EEMBC CoreMark benchmark shows 40 µA/MHz in active mode, with less than 900 nA and full 32 KB RAM retention and real-time clock and calendar, and 200 nA in the deepest sleep mode. Much of the power saving comes from the architecture that allows the peripherals — including timers, serial communications, and capacitive touch sensing — to remain powered and running while the rest of the system is in a lower-power mode.
Engineering samples of the SAM L21, along with development tools and datasheets, will be available in February.
The KW2x is running the Thread protocol that aims to make home IoT applications interoperable.
Thread has been set up by Google's Nest division to provide native IPv6 connectivity. It is based on the 6LoPAN variant of the IEEE802.15.4 standard, and Freescale is demonstrating its beta development kit for the first time.
The KW2x integrates a 2.4GHz 6LoPAN front end with a 50MHz Cortex-M4 CPU with DSP capabilities, up to 512 KB of Flash memory, 64 KB of SRAM, and 64 KB of Flex Memory (only on the MKW21D256V). Peripherals include USB, crypto acceleration, 16-bit ADC, and flexible timers.
The radio transceiver has up to -102 dBm receiver sensitivity, +8 dBm maximum transmit output power, and up to 58 dBm channel rejection with a peak transmit current of 17 mA at 0dBm output power, and peak receive current of 15mA in its low-power mode.
The MKW2x is packaged in an 8 x 8mm LGA with 63 total contacts and is available now.
The mixed-signal designer Semtec has paired its long-range wireless transceiver with Microchip's eight-bit PIC18 controller to create a low-cost, long-range node for the IoT in the unlicensed sub-GHz bands of 868 MHz, 915 MHz, and 400 MHz.
Semtec built a network across Munich for the Electronica show using 10 gateways controlling nodes around the city.
Semtec's LoRa star protocol can run on the 8051-based core to provide a spread spectrum link, rather than the more common FSK protocol. This allows the link to operate at 20 dB below the noise floor to get a range of up to 20 km.
The LoRa nodes are controlled by a gateway in a star configuration, rather than a mesh, and these controllers can adaptively change the power and data rate of the links. New controllers can be added to support more nodes, which can range from mobile tracking devices to industrial sensors or even sensors in wristwatches.
Semtec has also worked with IBM to develop the code for the LoRa MAC running ARM controllers, and it will release these through the mbed development environment for controllers from Freescale Semiconductor, NXP, and ST Microelectronics.
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