Just as its predecessors did, the LPDDR4 specification is aiming to double its data rates while slashing power consumption in half, but the first publication of the spec by JEDEC won't be until 2014. And even though LPDDR3 is still working to gain traction, most mobile devices (such as smartphones and tablets) are still equipped with LPDDR2.
The LPDDR4 Low Power Memory Device Standard, like its previous incarnations, will be designed to meet the performance and memory density demands of the latest generation of mobile devices, such as smartphones, tablets, ultra-thin notebooks, on the latest, fastest networks.
Hung Vuong, chairman of JEDEC's JC-42.6 Subcommittee for Low Power Memories, tells me the group is finalizing the definition of LPDDR4, and the goal is to publish the specification next year. JEDEC published an update to the LPDDR3 -- first published in the first quarter of 2012 -- in August 2013. The update supports a data rate of 2,133 Mbit/s.
Key features in the LPDDR3 specification include write-leveling and command/address training to allow the memory controller to compensate for signal skew while making sure data input setup and hold timing (as well as command and address input timing) requirements are met. An optional on-die termination feature enables a light termination to LPDDR3 data lanes to improve high-speed signaling with minimal impact on power consumption, system operation, and pin count. In addition, LPDDR3 features low I/O capacitance.
SK Hynix 8-Gb LPDDR3 memory module.
"The challenge for LPDDR3 was time to market," Vuong said. LPDDR2 was published and available to the market for three years before work was started for LPDDR3 in 2011. For LPDDR4, JEDEC is aiming to have twice the data rate at 3,200 Mbit/s over LPDDR3 while using 50% less power. "The challenge is how to achieve that energy reduction at 32 Mbit/s, and the sub-committee had to look at architectural, signaling, and voltage changes."
Beyond data rate and power consumption improvements, he said, there are three things device and system manufacturers need to understand regarding LPDDR4. First, there is the architectural change. For a LPDDR4 die, architecturally it is now a two-channel x16 DRAM. "The objective is to improve timing closure, as well as reducing internal DRAM die power."
The interface has been changed, as well, with new signaling defined for LPDDR4 using low-voltage swing terminated logic. The signaling is now defined at 350 mVpp max with configurable termination. In addition, data bus inversion has been added to improve signal integrity.
The third significant change is voltage; LPDDR4 has been defined to operate at 1.1 V, though migration to 1.0 V could be an option for the future if there is a need.
"Our goal was to double the bandwidth performance, but also we took a much harder look at the power usage," said Dan Skinner, director of architecture development at Micron Technology and a JC-42.6 Subcommittee member.
For mobile systems, power consumption is always the top priority when developing a memory architecture, he said, but for PC and server memory, power consumption generally trails cost and performance, though that is starting to change as datacenter power use becomes more important. In addition, battery form factors tend to be static, so it falls on the memory design to address power issues and strive for improvement.
Skinner said there is a minimum performance requirement that is targeted, "but once that performance level is reached, then doing so at the best power point is the top priority."
No firm date has been set for the release of LPDDR4. Vuong said JEDEC JC-42.6 continues its work, which includes extending LPDDR4 to 4,266 Mbit/s.
This article originally appeared in EETimes.