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Chip Spotlight: Monolithic 3D ICs

3D chips based on through-silicon vias (TSVs) have been in the works for several years, but apart from a few special applications they have so far failed to move into the mainstream. While TSV-based 3D has moved into the engineering stage, mass production remains a moving target, with early adopters favoring a so-called 2.5D technique based on an interposer technology.

Recent 3D developments by the San Jose, Calif., startup, NuPGA Corp., may soon change the dynamics. The firm claims to have invented a true monolithic technique for creating any type of 3D chips, threatening to render obsolete the current TSV technology designed to stack die. The technique was first shown in public in December at the 3D Architectures for Semiconductor Integration and Packaging conference in Burlingame, Calif.

According to NuPGA’s founder and serial entrepreneur, Zvi Or-Bach, the true monolithic 3D chips will offer a huge increase in connectivity over a die-stacked alternative. For example, its 3D IC fabrication techniques can be used to stack memory on top of a processor, to stack bit-wide memory chips into byte-wide configurations, or just to shrink the die of existing designs by optimizing chip area versus height.

Any number of chip layers can be composed, according to NuPGA, enabling general-purpose monolithic 3D to reduce chip areas by as much as three times over conventional 2D. The simplest way to create 3D chips is to fabricate the bottom chip as usual, cover it with oxide, then bond it to a similarly oxide clad giant-transistor donor chip, which can then be etched after bonding into individual transistors that are then interconnected with metallization.

The main problem, however, is that the temperature required to create the top layer silicon transistors is around 900° Celsius, a heat that will melt the already formed lower-layer transistors. NuPGA's technique sidesteps that issue by bonding a top wafer that has already had its high-temperature processing done, leaving only low-temperature etching and metallization to finish the 3D design.

To create 3D chip layers with n-type and p-type transistors, the donor chip must be fabricated with dummy gates that are then etched and interconnected after wafer bonding. In NuPGA's process, a sea of transistors is fabricated on the donor wafer, each with a dummy placeholder for its gates. A novel bonding step then aligns the chips with an effective accuracy of 100nm, allowing the top-layer transistors to be finished by etching out the dummy gates and adding the top metallization layer.

One further advantage of NuPGA's technology is the fact each stacked chip is only 50 to 100nm compared to the 50-micron thickness with conventional TSV stacked die, thereby allowing many more chip layers to be stacked. That said, as with all 3D chips, the more die there are, the greater the heat problem, and in this regard NuPGA's technique offers no fresh advantage. In NuPGA's words: “Designers just have to learn how to manage heat in 3D.”

The heat issue can only be solved by product architecture improvements, which place slow functional blocks, such as memory cell arrays, on top and high-speed logic, including sense amplifier, on the bottom substrate. This scheme cannot, however, be implemented with TSV because each memory cell on the top layer needs to be accurately aligned to bottom logic within a few nanometers, hence the advantage of NuPGA's technique.

So far, the market for 3D devices has been mainly limited to CMOS image sensors, MEMS, power amplifiers, and more recently FPGAs. Aside from the technical difficulties, the market has been held back by the lack of EDA design tools, complexity of designs, integration of assembly and test, cost, and lack of standards.

The market potential is huge, however, given the biggest market opportunities will be in portable electronic devices like cellphones, smartphones, and tablet computers. The chips used in these devices are already very power conscious and are often already “3D-stacked” today via wire-bonding to save space. Cost, rather than heat removal, will be the biggest challenge here.

— Malcolm Penn is founder and president of the UK-based research firm, Future Horizons. The company hosts its annual International Electronics Forum in Marrakech, Morocco, May 4 to May 6, 2011. The forum theme this year is “New Rules for Old… Achieving Success in the Age of Nano Tech.” Click here for additional information.

3 comments on “Chip Spotlight: Monolithic 3D ICs

  1. Mydesign
    March 2, 2011

       Malcolm, would like to share some of my knowledge in 3D chips with our readers. 3D IC's promise to solve the 2D communication bottleneck and it enables the integration of heterogeneous materials, devices and systems. There are mainly 3 approaches to realize 3D IC's like chip stacking, wafer stacking and full monolithic integration. Each approach is at a different level of maturity and offers various degree of improvement.

       Among them monolithic 3D approach is important, which offers a high density of device-dimension vertical interconnects and thereby facilitates the optimal assembly of transistors and interconnects in a 3D volume. (The performance advantages of such a technology can be demonstrated with a 3D-FPGA).

  2. Nemos
    March 9, 2011

    I think this promising technology will change the electronics as we all know it today, and will lead to new promising applications.The benifits will be more powerfull chip in less area.Maybe is the solution to overcome the Moore's law from getting old.

  3. davidladler
    March 22, 2011

    I would like to hear people's thoughts about inspection of 3D IC's.  

    In particular, is there a role for in-line x-ray inspection at high resolution?

     

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