DesignCon Revs High-Speed Engine

Many of the world’s top engineers in high-speed chip and board interconnects will gather next month at DesignCon. Here’s my take on the annual event’s top sessions.

I think DesignCon is all about pushing the envelope. Three sessions standout for me as clearly focused on pedal-to-the-metal engineering.

These days 56 Gbit/second links are at the limits of what’s possible for serial links. So I expect to take a seat in a Rambus session on serial interconnects at 56 Gbits/s and beyond.

Another evergreen topic is the transition from copper to optical interconnects. Silicon photonics has been getting a lot of attention for being in the vanguard of that shift given developments and acquisitions at companies including Cisco, IBM, Intel, and Mellanox. A session on the topic promises to be a frank exploration of the reality underneath the hype.

The final of my three top sessions is also about the copper/optical transition. A panel on optical backplanes pulls together an impressive group of system and component experts who I expect will give a realistic picture of what’s to come in the next year.

Not everyone lives at the bleeding edge. Just one step back from it, many engineers are trying to drive interconnects to 32 Gbit/s and beyond. That’s the topic of another one of my must-see sessions.

Also among the top talks in my book is a keynote from Thomas H. Lee of Stanford on “The First Transatlantic Cable and the Birth of Engineering.” I put this one in my just-for-fun category.

Next page: Signal, power integrity challenges

There’s no way anyone can see all the sessions at DesignCon, but here are another half dozen I hope to attend if I have time after the top sessions listed above.

Two concurrent sessions will drive me schizophrenic because they both promise deep looks into the signal and power integrity issues of life in the fast lane. One appears to focus on the board a.k.a. the channel; the other on high-speed test issues. They include a rich mix of experts from system, component, and consulting companies.

I like to get real-world insights from multiple perspectives, so a systems-level modeling session attracted my attention. Among its panelists are top engineers from AMD, Avago, and Qualcomm.

Three other sessions fall in my miscellaneous category.

A keynote on “Ten Commandments for Effective Standards” sounds like a fun walk down a familiar slippery slope. My colleague Suzanne Defree plans a talk on Next-Gen Engineering (I’m all ears, Suzanne), and the CTO of startup Keyssa will describe his company’s novel wireless interconnect.

To read the rest of this article, visit EBN sister site EETimes.

Want to learn more? Register now for DesignCon, the premier conference for chip, board, and systems design engineers. Taking place January 27-30 at the Santa Clara Convention Center, DesignCon 2015 features technical paper sessions, tutorials, industry panels, product demos, and exhibits.

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