EDA World Embracing IP Subsystems

After attending the 48th Design Automation Conference in San Diego last week, it was clear to me that the discussion around the trend towards IP Subsystems is real and has substance behind it. In fact, several IP and EDA vendors were discussing this idea, including Sonics, Synopsys, Cadence, Atrenta, ChipStart, and eSilicon, to name a few.

Jim Hogan, a veteran of the EDA industry, framed this issue succinctly in his panel discussion noting that the requirement by mobile and portable devices to be able to stream video files has driven today’s system-on-a-chip (SoC) to become a collection of subsystems. In essence, the SoC of five or six years ago has now become a system-level feature in today's highly complex silicon solutions.

This tremendous pace of integration can only be achieved through the use of IP. But this creates another problem for the designer — how to manage this integration process intelligently, efficiently, and within cost and design time budgets. Increasingly, for many designers, it has become very difficult to do this. There needs to be a way to increase the level of complexity in response to market requirements without increasing the cost and amount of effort needed to accomplish the design beyond a reasonable level.

The IP Subsystem is the answer. Reducing the level of effort needed, while increasing the complexity and functionality of the silicon, is what is powering the move to IP Subsystems by many vendors. Designers would rather work at the system functionality level instead of acquiring and assembling many discrete IP blocks to create the functionality they need.

This also opens the door for EDA companies to step up with new products and approaches to applications software design, test-bench creation, and integration of the requisite parts into a contiguous whole — a portion of the new business model the EDA industry has been seeking.

{complink 7526|Semico Research Corp.} has previously stated that there will be an IP Subsystem product announcement from one or more of the major IP companies before the end of 2011. I saw nothing at the Design Automation Conference to change that view, and it could even occur sooner than that. However, that is not to say that the term IP Subsystem was a topic in every discussion occurring on the show floor. We are not quite there yet, but that time is not far off.

The momentum is building nicely, and the conference reinforced my opinion that this is really happening. The introduction of new products all depends on the level of market pressure on IP and EDA vendors to create innovative solutions in answer to the real-world problems designers face. When pressure is high, we're likely to see a solution enter the marketplace.

7 comments on “EDA World Embracing IP Subsystems

  1. eemom
    June 17, 2011

    As the process node shrinks from 40nm to 28nm, it will enable companies to add more functionality to their system on a chip.  This has been the trend in the semiconductor market for as long as I can remember and it makes logical sense.  As we move forward, technology advances and companies are able to incorporate more functionality on a single chip.  EDA vendors are keeping up with the trend by offering verification software (IP) that continues to evolve to meet the needs of the ever changing SoC.  They play an integral role in the process that allows engineers to continue integrating functionality on their design while knowing that their design is whole and “verified”.

  2. t.alex
    June 18, 2011

    What is the concept of IP subsytem? What is it different from typical process of buying and integrating IP into your own silicon?

  3. Hardcore
    June 18, 2011

    Hi alex,

    Generally when you DIY, you have to build your own communication channels between system components, if you have a couple of IP components on a chip, it can be fairly easy, but once you integrate a few more ip blocks onto the silicon, then you have to deal with more complex communication, bus clashes, bus resets, bus hogging etc, and it an be a real pain, because if you get it wrong then the whole silicon run is basically useless.

    To make matters worse, many of these issues only highlight them self when the chip is heavily loaded or operated under unusual situations, really to link silicon IP you need a well established and well tested  internal bus system, many of the FPGA vendors already have IP that links into these standard bus systems (we are still talking about on silicon communitcation).

    However in the last few years there have been other  chip producers ,such as Cypress  and their PSoC®  System, see:

    Here we see a system where the user/designer can pull together system modules on a single chip, managed by a central bus  and all without really having to get into the messy business of actually designing that central bus, it is a bit like painting by numbers but with silicon, you get a certain range of limited colours, pull it together in a fixed way and then end up with a finished product, the really frighting thing is that now high school students have teh same design capability as topend engineers.




  4. t.alex
    June 18, 2011

    Hi hardcore, Thanks for the explanation. Just to clarify more on my understanding: is this all about standardized interfacing between IP?

  5. Hardcore
    June 19, 2011


    Well there are standards and there are 'standards', even the FPGA houses cannot agree on a single standard when they are supplying libraries for their own devices, in many cases the same IP can have a number of different  interface protocols. 

    Many of the vendors tend to provide IP cores that interface into communication busses that they have already coded and tested, whilst there are some industry standards for inter-peripheral communication , such as PLB (processor local bus) & ,OPB (On-chip Peripheral Bus) both by IBM and both commonly used in FPGA design for tying the various parts of IP to an on chip CPU, in some cases there are several revisions of the same standard and they are not always interchangeable.


    But yes this is again another attempt to try and get a general consensus on tying various vendors IP together with a single system, problem is, that what is good for one group of people(signal processing )is not necessarily good for another group (heavy data throughput to storage), we can see this by looking at some of the embedded CPU IP designs, many are loaded down with various different bus implementations, specifically because you cannot just stick all your various IP onto one standard bus system, that is how you end-up with bottle necks.

     Personally I'm beginning to suspect that some of the SoC vendors are going to make the same mistakes as the early FPGA suppliers did rather than take on board the last decade of so of the FPGA learning curve.


  6. t.alex
    June 26, 2011

    I am a bit confused if IP subsystem concept is trying to address the issue or just bring in another 'standard'.

  7. Hardcore
    June 26, 2011

    Another standard that is supposed to be more standard, its all about control and buy in.



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