While Lattice Semiconductor's main play in FPGAs has been the ice40 architecture it gained from the acquisition of SiliconBlue Technologies, the company's own MachXO family has been an important player in the low-end programmable market, where devices often still are referred to as PLDs. The MachXO3, introduced at the end of September, deserves more scrutiny than a tossed-off reference to “just another low-power PLD.”
There's been increasing discussion of the importance of I/O optimization and efficiency, and this forms the heart of MachXO3 features. MachXO always has been about bridging different environments, and the new generation is intended to run the gamut from mobile devices to datacenter switching platforms.
Thus, MachXO3 focuses on the Mobile Industry Processor Interface (MIPI), PCI Express, and Gigabit Ethernet. Hard IP blocks are used for the latter two standards, while MIPI uses a combination of hard and soft IP for the most efficient implementation of the standard. MachXO3 combines the interface cores with a switching fabric that operates at 150 MHz.
Brent Przybus, senior director of product and corporate marketing at Lattice, said that two factors make the architecture easy to use in rapidly changing end products. First, the power dissipation is as low as microwatts in standby. In addition, MachXO3 combines “hot-swappability” with multi-time programmability, meaning upgrades to systems can be made in the field, and chips can be configured from PROM or microprocessors.
These bridge devices are not large FPGAs — the density ranges from 640 to 22,000 logic cells. But devices in the family are offered in high volume for less than $1.00 each, putting the MachXO3 in the price range of typical microcontrollers. Lattice might have defined a winning architecture for glue-logic consolidation.
This blog was originally posted on EDN.