Gallium arsenide (GaAs) will soon outpace silicon (Si) as a higher-performance choice for implementing integrated circuits, according to POET Technologies Inc. of Storrs-Mansfield, Conn. The handwriting has been on the wall since the 1980s, according to Geoff Taylor, a former Bell Labs scientist and co-founder and chief scientist at POET.
According to Taylor, GaAs, as opposed to silicon, will boost electrical transistor performance while integrating optical circuitry capabilities. These qualities enable both higher performance and novel IC architectures, thereby extending Moore's Law indefinitely.
“Silicon digital logic hits the wall at 4 GHz, but we can produce small gallium arsenide analog circuits switching at 100 GHz today and 400 GHz in the not too distant future,” he told EETimes. “Plus POET fabricates optical emitters and detectors for on-chip optical interconnects.”
Combining standard logic with optical components on the same chip also changes the design methodology, prompting a collaboration with Synopsys Inc. of Hillsboro, Ore., to help design hybrid electro-optical devices. For instance, an optical loop achieves an ultra-low jitter oscillator with higher bandwidth than silicon, according to POET. By going to multi-wave lengths, POET also aims to build ultra-precise analog-to-digital converters by encoding voltages as wavelengths, resulting in higher resolution and bit rates with reduced power and fewer components.
and can reach higher frequencies.
Other advantages of III-V over silicon is its lower operating voltage — as low as 0.3 V with electron mobilities as high as 12,000 cm2/(V·s) achieved by strained quantum wells — lowering the power required to operate III-V chips by 10 times or more, according to POET.
Of course, GaAs wafers are more expensive than Si, but the next generation of Si is already using silicon-on-insulator with fully depleted (SOI-FD) transistors — a technology that costs almost as much as GaAs, according to Taylor.
Most III-V elements, including indium (In), gallium (Ga), arsenide (As), and phosphorous (P), have much higher electron mobility than silicon. Special fabrication problems — namely, the lack of enhancement devices for digital circuits and of the p-channel transistor for complementary design — have prevented them from already taking over silicon. However, POET has found a way to grow successive layers of InGaAs on GaAs wafers, each with a little more indium, until they achieve a substrate on which both n-type and p-type transistors can be fabricated.
The p-types could ultimately achieve about a 1,900 cm2/(V·s) hole mobility in the strained InGaAs quantum well, which is not as high a figure as the n-types, which achieve 8,500 cm2/(V·s). Both are higher than silicon, at 1,200 cm2/(V·s). POET has high hopes that it can eventually boost the n-types to more than 12,000 in order to realize extremely high digital logic rates with complementary HFETs.
Taylor had moved on to the University of Connecticut for several years before the Bell Labs patents expired on III-V chips. It was there that he resurrected the Bell Labs work but transformed it from a single n-channel-only electrical/optical (EO) technology into a dual-channel electrical/optical technology aimed at extending Moore's Law indefinitely well into the future for complementary electrical/optical circuits. He renamed the technology Planar Opto Electronic Technology (POET). The University of Connecticut is now assigned the patents, with POET the exclusive licensee.
For the full story, see EBN sister site EETimes .