After a few tough years, the semiconductor global supply chain is thriving and growing again. However, all of this goodness does not come without a new list of challenges and problems. For instance, there is a lot of growing interest around 3D-ICs — the latest and greatest technology path that promises to make a significant impact in many segments of the semiconductor market.
Opinions regarding the viability of 3D-IC as a broad-market technology range from guarded enthusiasm to blatant dismay. It is an exciting technology, but it has equally challenging hurdles to overcome if it is to move it from the world of potential to the world of high-volume production. Many companies are applying their collective engineering prowess toward making 3D-IC commercially viable, and to bring the associated manufacturing costs in line with required levels of profitability.
A breakdown of these elements is presented in Figure 1.
One of the big challenges facing 3D-IC is that it appears that many of the tried-and-true methods in process technology, design and testability, and ATE may not be enough to achieve the desired effective cost necessary for broad adoption. Historically, test data has primarily been used in a post-manufacturing role, but it will need to play a much larger position when it comes to 3D-ICs.
The component margins in 3D-IC are not and very likely will not be very generous for the foreseeable future. This means that the management of manufacturing test parameters will play a significant role in the successful and profitable manufacturing of 3D-ICs. In this scenario, and understanding the compounding effect of yield loss in the multi-die architecture of a 3D-IC, the need to do smart pairing and smart screening of devices takes on an even more important role.
Commercial solutions are already providing increases of up to 3% in recovered yield in single die manufacturing by applying manufacturing intelligence across test operations. With the multiple dice involved in 3D-IC design, there can be a compounding benefit by leveraging that same level of intelligent data for all the devices in a 3D-IC package. As depicted in Figure 2, this includes not just aggregating data from the different processes, but correlating that data across all elements within the test spectrum to achieve the best possible results for a given 3D-IC design, thus lowering the overall effective cost.
Probably the most challenging aspect of manufacturing and testing 3D-ICs centers on stack failure and performance. Having multiple good dice connected together and stacked into one package can create problematic combinations including:
- Dice incompatibility within a specific parameter, e.g. four stacked Bin1 dice with large variability in power consumption
- Dice incompatibility between parameters and augmented test data, e.g. dice with low power but high latency
- Correlation of dice interdependencies, e.g. thermal dissipation effects
To confront and eliminate the above effects and achieve the lowest effective cost, it is essential to apply intelligent and smart pairing mechanisms that take into account the overall augmented test data across the full virtual supply chain: expanding from eTest, wafer sort, and burn-in for all participating dicehomogenous and heterogeneous, up to final test and SLT test data of the stacked package.
It should be noted that all of the participating dice data from various IC vendors (for example, memory ICs) need to be included as part of these operations. All of this information should be in one robust and intelligent system to achieve the lowest effective cost for 3D-IC manufacturing.
As the semiconductor industry has successfully done for decades, it will continue to find new ways to follow Moore's Law, including improving on the hard costs involved in manufacturing 3D-IC designs. However, in addition to improving the fixed costs of 3D-IC manufacturing, it is also important to look for ways to improve the effective cost, which will speed the market adoption of 3D-IC.