SAN JOSE, Calif. — Traditional semiconductor scaling is expected to reach an end by about 2024, according to a white paper from engineers working on a new version of the semiconductor roadmap. The good news is a wide variety of new kinds of devices, chip stacks and systems innovations promise to continue benefits in computing performance, power and cost.
“Die cost reduction has been enabled so far by concurrent scaling of poly pitch, metal pitch, and cell height scaling. This [will likely] continue until 2024,” according to one of nine white papers published today as part of the International Roadmap for Devices and Systems (IRDS).
Beyond that date “there is no room for contact placement as well as worsening performance as a result of contacted poly pitch (CPP) scaling. It is projected that physical channel length would saturate around 12nm due to worsening electrostatics while CPP would saturate at 24nm to reserve sufficient CD (~11nm) for the device contact providing acceptable parasitics,” the white paper reported.
The IRDS is an expanded version of the International Technology Roadmap for Semiconductors (ITRS), first published in 1965. The effort was taken over by the IEEE in May last year when it was renamed the IRDS and expanded to cover new kinds of system-level technologies.
The IEEE expects to release the first formal version of the IRDS at an event in November in Washington D.C. The new white papers represent an interim step toward that update.
Many of the white papers carry on the traditional work of the ITRS looking at areas such as CMOS scaling, emerging devices and yields. A handful of the papers break ground in new areas such as system interconnects and new kinds of computers such as quantum and neuromorphic systems.
Of all the while papers, the so-called “More Moore” article is the most detailed. It provides a wealth of information on expected dimensions and materials for logic and memory devices as well as their key components such as interconnects.
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