Top 9 Chip Design Challenges

As we evaluate the system-on-a-chip (SoC) design landscape, the industry continues to search for solutions to a long list of design challenges and issues. They include the following.

  1. Rising cost:
  2. SoC silicon and software design costs are rising at each new process node, with increasing emphasis now being placed on the software side of the design cost equation. How can we reduce design costs, especially for software, in a meaningful way?

  3. Design complexity:
  4. Complexity is increasing to meet rising market requirements. How can SoC designers continue to meet these rising demands without “breaking the bank” through higher design costs, or missing the market window altogether because of long design cycle times?

  5. Power consumption:
  6. This continues to be the major issue for designers today — especially in light of the trend for users to have hundreds of apps on their mobile devices. What methods are available to reduce power consumption and still meet consumer expectations and market requirements?

  7. Integration cost:
  8. The cost to integrate the large number of IP blocks being used in SoCs today is rising, and this is probably one of the causes of increasing design costs in general. How can IP integration costs for complex SoC designs be curtailed or even lowered while still infusing added functionality into these designs?

  9. Testing and verification:
  10. The difficulty in achieving timing closure and running verification for complex SoC designs are other troubling trends designers must contend with. Are there any solutions today that reduce the level of effort needed to reach timing closure and that make the verification process easier?

  11. Return on investment:
  12. Rising design costs for SoCs increase the number of parts that need to be sold just to make back the design investment. How can SoC designers reduce the level of effort needed to create the system-level functionality needed for their silicon solutions and still reach performance and functionality targets set by the market?

  13. Performance and latency:
  14. The multicore era is firmly with us, and performance issues, especially in the area of memory latency, continue to get worse. Is there any solution on the horizon that can finally reduce memory latency and break the “memory bottleneck”?

  15. Efficiency issues:
  16. The number of IP blocks in complex SoC designs today is approaching 100, if it hasn't already exceeded that level. This adds to design complexity and cost. How can SoC designers test out different types of IP cost-effectively and efficiently?

  17. Identifying new markets and applications:
  18. Silicon foundries continue to push the process technology envelope at each new node, but the cost for doing so is rising as it becomes more difficult to advance. What new markets and applications will drive wafer starts at 20nm and at 14nm?

This is a pretty long list of issues and questions that the industry needs to work through. Many of them are not new, but it certainly feels as if they are becoming more intense in their nature and importance. This is one of the reasons {complink 7526|Semico Research Corp.} decided to host a conference on the IP ecosystem. Since IP has assumed such a critical role in the SoC design methodology today, Semico has created a forum that brings together concerned parties to discuss these issues, their impact on the industry, and their potential solutions.

The Semico Impact Conference, titled “Focus on the IP Ecosystem,” is taking place on May 16 in San Jose, Calif. Speakers from across the industry will address some of the challenges and issues raised above.

EDA tool vendors, silicon foundries, FPGA vendors, IP vendors, and IDMs and OEMs will present their ideas about the path the industry is taking, or should take, to resolve these questions. All these companies are intimately involved in the IP ecosystem directly or are touched by it indirectly to the point that any potential solutions will probably start as ideas conceived in private but discussed in public, to gain insight into just what SoC designers and silicon architects are thinking about.

Just the topic of the trend towards IP subsystems alone could take up an entire day, given the complexity of the issues involved. The potential of IP subsystems to provide real solutions to some of the issues and questions listed above makes discussing this subject a real imperative for the industry. A healthy debate on these issues is necessary to gain industry consensus and support in order to chart a course that will provide the best possible outcome for all involved.

If you are a SoC designer and have an opinion about some of the questions listed here, you should attend, discuss, and learn what solutions are being proposed. Make your voice heard, and hear from others. If you are a silicon architect and wonder how you are going to be able to squeeze all the functionality needed into your next design in less time and at a lower cost, you should attend and help shape the future through your input and comments.

If you are a silicon or software engineer and have noticed how it is getting harder to keep coming up with new solutions to old problems, you should attend to find out what ideas are being proposed to actually help put some of these issues behind us. We think this conference will provide a vehicle for many concerned parties to come together and have the opportunity to hear about the problems that have been identified, what we should be prepared for, and learn about real solutions that can move the IP ecosystem forward toward potential resolution of these issues. That would be worth the price of admission alone.

We hope you agree and look forward to seeing you at the Doubletree Hotel in San Jose, Calif., on May 16. For more information on the conference visit Semico's Website, or register here.

10 comments on “Top 9 Chip Design Challenges

  1. t.alex
    May 4, 2012

    Given the amount of challenges, it is really not easy to deliver a product on schedule  to target specific market demand. In parallel to the SoC development, firmware, operating systems, software must come along. This is definitely problematic as there is no stable SoC yet for software development and hence the development process must come hand-in-hand.

  2. Rich Wawrzyniak
    May 4, 2012

    Hi t.alex,

    One of the areas that we will discuss at the IP Ecosystem conference is the impact of IP Subsystem products on the SoC design flow. As you correctly point out, the software side of the SoC design equation has started to become the largest portion of the cost associated with these designs. One of the attractions to using IP Subsystems is the ability to write the software application that will be executed by that subsystem independently of the other applications to be created. Because the IP Subsystem is a complete system-level function (and not a collection of descrete IP blocks aggregated together), it is possible to write the software app before the silicon design is done. if there is more than one IP Subsystem in the design, then the software applications can be written in parallel. Based on current trends where software designers outnumber silicon designers on large SoC designs, I have to believe that the ability to write the software apps in parallel, and not serially, will allow total software design time to be reduced, this can reduce costs and accelerate time to market.

    To your point about not having a stable SoC to write the application for: the IP Subsystem can stand in for large parts of the SoC since it is a system-level function that has already been tested (delivered with its own testbench) and could quite possibly come with application code already written for it. Take a look at the Audio IP Subsytem introduced by Synopsys at the end of March. It comes with >500K lines of application code. Other subsystem products are coming and they will probably come with their own application code as well. It depends on the function and what the function requires at the system level as to how many lines of code will be attached to the subsystem.

    Thank you for your question, It goes to the heart of the issues surrounding the rising costs and complexity of the SoC design flow today. I am sure we will see other products that start to address these questions and issues – maybe announced at the conference!

    Best regards,

    Rich Wawrzyniak

  3. itguyphil
    May 6, 2012

    Hand-in-Hand with what? Is it the people or the processes within the disparate systems?

  4. t.alex
    May 7, 2012

    porchale, hand-in-hand between SoC and software. They need to be built for each other step by step.

  5. t.alex
    May 7, 2012

    Rich, thanks for the detailed explanation. As you have clearly illustrated, this addresses most of the major issues when it comes to complete SoC system design. And it also releases the creativity from the software people. 

  6. Anand
    May 11, 2012

    What methods are available to reduce power consumption and still meet consumer expectations and market requirements?

    @Rich, thanks for the post. One of the major changes that the companies are implementing is they are trying redefine the old architecture so that they can reduce the chip-area. I have seen many digital libraries where the companies have achieved as much as 40% reduction in power by redefining the architecture.

  7. itguyphil
    May 12, 2012

    Interesting. I wonder how seamless that process can be. Especially when there needs to be clear communication channels among the two teams. Have you seen this implemented successfully?

  8. Wale Bakare
    May 12, 2012

    What methods are available to reduce power consumption and still meet consumer expectations and market requirements?.

    I think that remains heavily on amount of energy the RF baseband of the system design would consume.

  9. Rich Wawrzyniak
    May 12, 2012

    Hi Pocharle

    You ask a very interesting question. Today there are two sources of IP Subsystems – large IDMs that have created them internally and, just starting now, the 3rd Party IP market.

    Large IDMs do not talk much about their internal efforts because they are being used to competitively differentiate their products from their competitors. A secondary result is to reduce the level of effort necessary to create the system-level functionality needed for thier complex SoC products. The 3rd Party IP vendors are just starting their marketing efforts.

    To answer your question directly: no, there is no direct evidence that this approach has been implemented effectively. That is to say no one is trumpeting this result – yet.

    Having said all that, I would like to point out that the large IDMs would not be pursuing this course if there were not tangible benefits to doing so. Companies like Intel, Qualcomm, Broadcom, ST Micro, Toshiba, TI and I suspect Apple as well, and many others, have all created their own IP Subsystems and use them in their design efforts. Although there is no direct evidence of how seamless the process is between the HW and SW teams, I think it safe to say that where there is some smoke there is probably some fire as well.

    I would imagine that the process is not totally painless. There needs to be a willingness on both sides to collaborate to solve real issues and problems that prevent designs from being accomplished more efficiently and at less cost. I think if this approach is taken by all concenred, then great strides can be made in reducing the level of effort necessary to create the complex silicon solutions the market requires today.

    To me, it is all about the silicon (meaning the final solution at the system level). If the silicon is not competitive in the market because the design was too expensive, or took too long to complete, or does not perform as expected or the software does not run as expected, then it is all but useless. It is very counterproductive to point fingers at different groups within a company when the esults are poor. The net result is that the product does not live up to expectations and everyone at that company suffers – even upper management!

    I believe this is why the IP Subsystem concept has a chance of succeeding in the market. If implemented correctly and efficiently, it offers solutions to many of the issues I raised in the original post. Thre are other potential solutions for these issues, but they are more complex to implement and more costly. Here I am thinking of things like less leaky transistors, or better and more powerful tools for doing the design.

    The problem with creating a better process technology or investing in better tools is that the industry is already doing that and has been doing that for at least the last 10 years, yet the problems are still with us and are arguably getting worse. The reason for this I believe is that these approaches are trying to hit a moving target that is accelerating as time goes on. A better approach is to allow design teams to craft their silicon solutions using larger pieces of the puzzle in the form of complete system-level functions and to allow the software teams to write the applications code specifically to each IP Subsytem. Then, assuming there is more than one IP Subsystem in the silicon, the applications can be written in parallel. This potentially can dramatically reduce both design time and cost while allowing better code to be written.

    The devil is in the details. This approach will certainly not be easy but I believe it is possible if care is taken in how the infrastructure is created and if people are committed to getting this done.

    I know this is a very long answer to a relatively short question, but as you can see, this issue is pretty complex.

    Thanks for your interest!

    Best regards,



  10. itguyphil
    May 15, 2012


    Thanks for the reply. One point you made was interesting:

    “It is very counterproductive to point fingers at different groups within a company when the esults are poor”

    I think this is always an internal battle since teams are disparate in most organizations and feel accoutnable for their own tasks at the micro level and not necessarily the macro level as a whole organization. This has to be one of the biggest things that can throw a wrench in any product development's success. This is where a unified company culture is vital… and usually not stressed enough.

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