TSMC Expands its 3D Menu

SAN JOSE, Calif. – Taiwan’s largest semiconductor kitchen released its latest menu, a 3D matrix that spans process, packaging and applications-specific options.

TSMC described at an event here FinFET processes down to 7nm it will serve up over the next few months as well as an expanding set of 3D packaging options. “We are getting into a 3D x 3D era that will carry us into the next decade, said Jack Sun, chief technologist and vice president of R&D at TSMC.

The foundry will have volume production of its 10nm process before the end of the year and be ready to take orders for its 7nm process by April, said Sun. He showed two new variants in the works for the so-called InFO stacks analysts say Apple is now using for its A10 Fusion SoC. And he sketched out a handful of other 3D packaging options for different uses.

The processes and packages are being supported across design platforms being tailored for four markets. “From this year, beyond an enhanced mobile platform we will add design platforms for high performance computing, automotive and the Internet of Things,” said Cliff Hou, vice president of R&D for design technology platforms at TSMC.

The high performance computing (HPC) platform promises 1V processors running at 3.8 GHz data rates in the 7nm process. The IoT platform will approach but not embrace near threshold voltages, and its cousin for automotive will support chips rated to an operating temperature of 150 degrees C.

One fabless engineering manager expressed an enthusiastic appetite for the breadth and variety of combinations now available at TSMC. “Imagine what you could do with it…it slices across technology barriers,” said Michael Campbell, a vice president of engineering at Qualcomm, noting–for example–the potential to mate an SoC to a CMOS image sensor for use in robotics.

TSMC is essentially cranking out a new process every year. Its 28+ HKMG and 16FF+ processes are in production now, and the 16FFC and 10nm processes are ramping this year. Yields for 256 Mbit SRAMs at 7nm are two months ahead of plan with risk production starting in the first quarter of 2017, said Sun.

The 16nm processes provide about 45% more speed and 80% less leakage than 28+ and support four voltage levels, TSMC said. The 10nm process provides a 50% die scaling and 50% speed gain or 40% power reduction over 16FF+ and provides “the highest density in the industry today in contact pitch,” said Sun.

Compared to 10nm, TSMC’s 7nm node delivers 15-20% more speed or 35-40% less power consumption and a 1.63x better routed gate density, said Sun. An ARM Cortex-A72 core in the 7nm process could deliver 30% more performance or 56% less power consumption than in 16FFC, said Hou.

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